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서정훈 박사
ASML US
Introduction to Optical Lithography
This course will introduce basic knowledge and concepts of semiconductor lithography. Audience will learn the lithography process flow and basic optics in it, then, a few important metrics and how computational lithography can help it.
1. Background
2. Lithography process
3. Optics behind the semiconductor lithography
4. Key metrics in lithography
5. Computational lithography
6. Challenges in lithography
7. Summary
Jung-Hoon has extensive knowledge in computational lithography with lots of field experiences. In Samsung semiconductor, he was one of the key members of the logic device OPC, RET, and DTCO (Design-Technology Co-optimization). Recently in ASML, he worked on EUV SMO, scanner imaging studies, DTCO, and OPC product development and improvement.
He is currently working on ASML's SMO product which enables the leading-edge RET in both EUV and DUV lithography technologies for logic and memory devices.
- 2021 ~ Current
Principal Architect, SMO Product Engineering Group, ASML Brion, San Jose, CA USA
- 2016 ~ 2020
Manager of OPC Product Engineering Group (Customer Focus), Principal Engineer, ASML Brion, San Jose
- 2014 ~ 2016
Principal Architect, ATD team, ASML Brion, San Jose
- 2007 ~ 2014
Principal Engineer (수석 연구원), OPC team, SRD (Research center), Samsung Electronics (Semiconductor), Korea
- 2001 ~ 2007
Principal Engineer (수석 연구원), Opticis, Korea
- 1995 ~ 2000
Ph.D. in Physics, KAIST, Korea