| 2nd Day | Aug. 13, 2024 (Tue.)
LO-I
Layout Optimization and Computational Lithography-I
405/406
13:30~15:00 KST
좌장: 양현조 (ASML)
LO-I-1
Rigorous 3D Probabilistic Computational Lithography and Chip Level Inspection for EUV Stochastic Failure Detection
*김은주 (삼성전자)
Abstract
13:30~14:00
LO-I-2
Expansion of Machine Learning Solution in OPC
* 김성호 (SK hynix)
Abstract
14:00~14:30
LO-I-3
300mm size Wire grid polarizer(WGP) manufacturing method using 50nm line pattern stitching process technology in ArF immersion
*송정철 (National NanoFab)
Abstract
14:30~15:00
