Abstract
Plasma has been widely used in the semiconductor processing for decades due to its many proper properties for processing. Plasma makes processing fast and enhances vertical profiles. Additionally, plasma processing enables low temperature process which is crucial for decreasing heat budget to the semiconductor devices, and improves the particle problems falling to the wafers. For these reasons the plasma has expanded its regime in the semiconductor processing to all the area of processing. Due to its key role in the process, there have been many researches to find the most suitable plasma for each process. For example, there were many researches to adapt the high density plasma sources like ICP or helicon to the oxide etching, but most of them failed and there were least trials of that these days. Instead, other researches for various kinds of pulsing have been successful and are widely used in the business. In this presentation I will review the history and the current status of the plasma processing in the semiconductor business and wish to discuss what will be necessary in the future in the plasma processing  


Biography
Dr. Bai is a V.P. of tech (Master) in Samsung semiconductor R&D center. He has worked with responsibility on developing patterning since 2002. Recently he is leading EUV patterning in the R&D center. He received a Ph.D degree in plasma physics from KAIST, Daejeon, Korea. His Ph.D thesis was controlling the plasma parameter using a biased grid and gas mixing. He has published more than 50 papers and patents on his research area.

 

Abstract


Light is the critical driver for leading-edge semiconductor manufacturing. The properties, quality, and quantity of light at specific wavelengths determines the manufacturable device performance and economics.
Therefore, innovations in light source technology fuel our modern economy. Photolithography is the quintessential innovation cycle between light source and manufacturable transistor; however, this trend is now evolving more rapidly in metrology and inspection as device critical features approach near atomic dimensions, architectures evolve to three dimensional geometries, and cycle time between nodes and products must keep pace.

Particle accelerators offer the means to construct multifaceted, utility-scale light sources with unprecedent manufacturing capability that can dramatically reshape the economics beyond the semiconductor industry. Cost and capability scaling of lithography driven by a free - electron laser would drastically alter the economics of Moore’s Law as we know it, and the advances in wavelength, resolution, sensitivity, and throughput in metrology and inspection applications would similarly reshape the research, development, and process control strategies. The paradigm shift of accelerator-based light sources will be the most dramatic shift in semiconductor manufacturing history, and the reverberations will affect both parallel and tangential industries.


Biography


Erik Hosler has founded several companies, including FylEx and xLight, organizations focused on industrializing particle accelerator technology and the associated applications to deliver a paradigm shifting light source technology for semiconductor manufacturing and beyond. Erik received his PhD from the University of California, Berkeley in Physical Chemistry, and afterwards he went into lithography research and development at GlobalFoundries, eventually leading the industrialization program of EUV lithography. He has published a variety of technical papers on lithography and light source technology, including on industrialized free-electron lasers. Erik also worked at PsiQuantum as the lithography and patterning strategist for initial silicon photonic quantum computing test vehicles before starting xLight and FylEx to drive the industrialization of novel light source architectures.

Abstract


In the rapidly evolving field of semiconductor devices, significant technological milestones have been achieved for DRAM, Flash, and Logic devices. This talk will provide a historical overview of these developments, tracing their technological advancements and examining the metrology and inspection (MI) technique, one of the key technologies that enabled such advancements. Furthermore, we will also examine the current challenging MI issues related to semiconductor devices and the recently introduced advanced packaging (AVP) process. One of the goals of this talk is to provide a comprehensive overview of the various challenges encountered and explore potential solutions to address these issues, particularly from the perspectives of detecting nano-sized pattern defects and measuring nanostructures. This will involve a detailed analysis of the current state-of-the-art MI technologies, as well as an evaluation of the potential benefits and limitations of recently emerging AI-based approaches for addressing these challenges. A comprehensive view of the developmental trajectory of MI technologies, covering its fundamentals, challenges, and future expansion will be covered in the talk in detail.


Biography


Yusin Yang, is Fellow and has been working in SAMSUNG Electronics CO. since 2000. He received B.S. and M.S. in Physics at KAIST(Korea Advanced Institute of Science and Technology) in 1993 and 1995. And in 2000, he received his Ph.D. from KAIST with a dissertation on crystal growth and characterization of KTiOPO4(KTP) isomorphs.

Since joining Samsung Electronics CO. in 2000, he has worked on developing MI (Metrology and Inspection) technology for memory semiconductor device by 2019 and has expanded his work into logic device since 2020. Now he is responsible for establishing MI technology strategy for the entire semiconductor devices after being appointed as company Fellow in 2022.

His research focuses on in-line MI technology to detect nano-size defects and measure sub-nano-size patterns structures especially for the next-generation semiconductor devices. The technology includes various microscopic areas from optical to electron microscope expanding applicable spectral range. In optical microscope his study has been focusing on developing the contrast enhancement technology for the virtual resolution enhancement. In electron microscope he is developing multi-beam technology to overcome the disadvantage of electron beam scan speed. In order to measure subsurface nano-size structures, conventionally SE(Spectroscopic Ellipsometry) and high voltage SEM(Scanning Electron Microscope) technologies are used. For more development of those technologies he is studying advanced RCWA(Rigorous Coupled Wave Analysis) method with AI(Artificial Intelligence) algorithms. As a future application using SEM technology, his study includes three-dimensional SEM concept development.

He has more than 140 patents and has authored or coauthored several papers in the field of semiconductor MI technology. For the future, he is trying to develop innovative MI methodology which can be the potential for the next generation 3D semiconductor devices.

Abstract


The extension of the 2D baseline platform in DRAM devices is facing challenges caused by the limitation of patterning and device performance. The adoption of new lithography technologies for Stack-Up structures in NAND devices are being necessitated due to the evolving patterning process. Especially, In the DRAM devices, the on-going development of various lithography technologies aims to decrease CapEX and OpEX for Extreme Ultraviolet (EUV). Moreover, it is crucial to define and prepare lithography technologies that incorporate advanced concepts in alignment with the shift towards new technological platforms such as VG or 3D-DRAM. In order to thrive in this industry within a continuously evolving ecosystem, it is imperative to develop photo process technologies that prioritize maximizing the EUV applications including High-NA EUV, advancing OPC (Optical Proximity Correction) technologies, optimizing patterning process through advanced metrology analysis methods based on Big-Data and creating breakthrough technologies to address the limitations of overlay correction capabilities. Moreover, establishing an assertive collaboration model with business partners and innovating the methodologies within R&D are essential in developing equipment with newly introduced concepts. This lecture will explore the challenges and future directions of photolithography technologies, based on insights from the industrial perspective within the memory market sector, considering key aspects of the technological roadmap.


Biography


Jaewook Seo is the vice president of R&D photo process department at SK hynix. He received B.S. in ceramic engineering from Yonsei University in 1998. After joining SK hynix in 1998, he participated in the development of DRAM photo process for various generations of tech. node. He was appointed as vice president of R&D photo process in 2022 after serving as the head of the advanced photo team in 2019.
Currently, he is in charge of research and development of photolithography roadmap for DRAM, NAND, and new memory devices. His research focuses on developing new patterning technologies in preparation for the transition of DRAM to new platforms such as VG/3DDRAM and overcoming the limitations of DRAM/NAND patterning. He is also in charge of developing advanced OPC technologies such as High-NA EUV OPC and ML based OPC applications from 2023.

Abstract


Lithography resolution has been driving dimensional scaling of semiconductor devices, but nowadays it is more and more complemented with device level 3D architectures (such as Gate-all-around) and system level 3D integration (such as stacked SRAM on Logic  and 3D DRAM on Memory). Logic backside power delivery network (BS-PDN) is a disruptive innovation that offers significant performance gain in combination with higher transistor density. Key feature of this technology is the ability to connect to the already fully processed front-end devices from the backside. This connection takes place after fusion bonding and requires, depending on the chosen process flow, a single digit tight post-bonding scanner overlay control.
In this presentation, we will discuss implications of the BS-PDN processing on scanner alignment, overlay metrology, and overlay control for the post-bonding exposures. We will show that a significant improvement is possible to meet the overlay performance requirement by applying high order corrections per exposure of the scanner and we will discuss additional opportunities to improve the performance. We will pay special attention to the wafer edge (R > 135mm) as in this region it will be most challenging to achieve the required post-bonding overlay


Biography


Nak Seong is Director of TDC US/Asia of ASML. He joined ASML TDC, Technology Development Center, in November 2013. His work covers studies of future semiconductor technology trends to understand requirements of future patterning technologies. From 2007 to 2013, he worked at Cymer guiding product developments and driving customer interactions by analyzing patterning impact of light sources. From 2001 to 2006, he worked at IBM where he worked on high NA imaging, 157 lithography development, and DFM for low k1 imaging. He started his career at Samsung in Korea in 1989 where he developed lithography processes for DRAM in early days, and developed RET for low k1 imaging solutions for memory products and scanner evaluation methods to support them. He graduated Kyung-Hee university in 1989 with BS in Physics.

Abstract


Embarking on a career journey towards Silicon Valley is like setting off on an adventure into the heart of innovation and opportunity. In this keynote, we'll break down what Silicon Valley is all about, focusing on its semiconductor industry and the exciting world of artificial intelligence. We'll cover everything from the history and main players to the unique culture that sets this place apart.
We'll dive into the corporate world of semiconductor giants and explore the various career paths available, whether it's sales, marketing, engineering, or something else. And we'll stress the importance of networking, showing how making connections can really boost your career prospects.
Drawing on my own experiences over the past twenty-eight years, working at companies like SVG, ASML, Therma-Wave, Integrated Materials, and KLA, we'll look at how I got to Silicon Valley and what I learned along the way. We'll talk about key moments like company acquisitions and moving internationally, and I'll share some tips for navigating these challenges.
But here's the thing: there's no magic formula for success in Silicon Valley. It takes hard work and planning. So, I'll encourage you to start thinking about your future now – not just in vague terms, but with specific goals for where you want to be in one year, two years, five years, and beyond.
And remember, networking is key – both in Silicon Valley and wherever else your career may take you.
So, join me as we embark on this journey to Silicon Valley, where every challenge is an opportunity and every connection can make a difference.


Biography


Simon Lee is the Chairman of KASASV(Korean American Semiconductor Silicon Valley), non-profit organization in Silicon Valley. He is a seasoned professional with over twenty years of experience in the global semiconductor industry, specializing in sales, business development, and strategic leadership. His career in Semiconductor Equipment Industry started from SVG, ASML, Thermawave, Integrated Materials, and KLA and led Corporate Sales from HQ to Korea region as well as Worldwide region depending upon roles at each company and has broad range of semiconductor process equipment experiences from Photo, Litho, Diffusion, APCVD, Metrology and Inspections. He holds MS in MIS and MA in Computer Education from USIU(a.k.a. Alliant Int’l University).