Abstract

EUV lithography has been showing big improvements since the first 0.33NA tool released at 2013, and is going to be widely used for DRAM and logic devices trough devices scaling down. Therefore the importance of EUV productivity is growing continuously for volume production. There are several key factors to improve it, for example tools stability, factory automation, increasing throughput and so on.
Among them, the process optimization to reduce Dose-to-Size is the one of the powerful method to increase EUV productivity by using the inside and outside lithography eco-systems. In this paper, what kinds of eco systems have been used and are being prepared currently to improve EUV productivity.

Biography

Up to last year, “Keundo Ban”, had been the head of EUV material and process team for 6 years in SK hynix EUV TF and nowadays, is responsible for EUV resolution enhancement and high NA EUV development. Ban and four others received the Innovation Award from SK Group in 2024.

Abstract

EUV pellicles are critical components for improving yield in EUV lithography; however, their development has faced significant challenges due to material limitations. This presentation reviews the current status of EUV pellicle material development in response to the advancement of EUV exposure tools and discusses strategies for successful pellicle implementation. In particular, the properties of graphite and molybdenum carbide materials developed by the EUV Pellicle Consortium will be introduced, along with recent research findings on carbon nanotube (CNT) materials, which are emerging as promising candidates for next-generation pellicles. By comparing the advantages and disadvantages of each material, we aim to identify effective pellicle material strategies and discuss process technologies necessary for mass production.

Biography

Hyeongkeun Kim is a Project Director at the Korea Electronics Technology Institute (KETI), where he has been working since 2011. He received his B.S. and M.S. degrees in Mechanical Engineering from Sungkyunkwan University (SKKU) in 2003 and 2005, respectively. In 2011, he earned his Ph.D. from SKKU with a dissertation titled "Development of Roll-to-Roll Based Large-Area and High-Purity Graphene Synthesis Technology Using Chemical Vapor Deposition."

  After completing his Ph.D., he began his career at KETI as a postdoctoral fellow at the Electronic Materials & Device Research Center. Since 2011, he has served as a Principal Researcher at the same institute. In 2020, he was appointed as the Project Director of the EUV Mask/Pellicle Materials Research Project at KETI.

  His team focuses on the development of metal oxide film coating equipment and processes based on atomic layer deposition (ALD), aiming to enhance the safety and efficiency of semiconductor and display manufacturing. Their research also includes AI-based process prediction and the development of film deposition processes involving materials such as graphite, molybdenum, and yttrium for use in EUV pellicle and mask fabrication for semiconductor lithography.

  Dr. Kim holds more than 190 patents and has authored or co-authored 54 papers in the field of semiconductors. Looking ahead, he is committed to developing innovative pellicle technologies with the potential to support next-generation high-NA EUV scanners.

Abstract

In line with the development of high-power EUV light sources, the development of a carbon-based pellicle with high transmittance and high thermal stability is drawing attention. Since most carbon-based pellicles have a porous structure, the transmitted light can be scattered. Therefore, ASML has recently added transmission scattering (flare) to the optical KPIs (Key Performance Indicators) for the next-generation pellicle. This year, Pohang Accelerator Laboratory (PAL) has developed an EUV pellicle evaluation system to meet the demand for next-generation pellicle evaluation.

In this talk, we will discuss the optics and specifications of our pellicle evaluation system at the PAL, as well as the test results for three types of pellicles. Our system can measure the transmission, reflection, and flare of the pellicle at an angle of incidence of 6 degrees. The evaluation accuracy, both for reflection and flare, is 0.0001% relative to the transmission. The detection angle for the scattered beam is adjustable in the range of 0 to 60 degrees. In addition, to accommodate the evaluation of developments of various sizes, it is designed to evaluate from a coupon size to a 6-inch full size. The three kinds of pellicles used in the first test are metal-based, metal-coated carbon-based, and carbon-based materials. As a result of the evaluation, changes in transmission, reflection, and flare due to pellicle defects and material properties were successfully observed. Also, we confirmed the high reliability and reproducibility of our system through repeated measurements.

Biography

Jiho Kim is a staff scientist for the EUV beamline in Pohang Accelerator Laboratory (PAL). He earned his Ph.D. in Physics from the University of Seoul (UOS) and completed postdoctoral research at the 12D IRS beamline in PAL. Currently, he is focusing on the testing and evaluation of materials and devices for extreme ultraviolet lithography (EUVL), including EUV photoresists, masks, and pellicles.

Abstract

Extreme ultraviolet lithography (EUVL) is pivotal for advancing semiconductor manufacturing under 5nm technology nodes. This paper explores the integration of low-n attenuated phase shift masks (att-PSM) and advanced source mask optimization (SMO) technis to address the fundamental challenges posed by EUV lithography, particularly mask 3D (M3D) effects which degrade image quality due to phase errors induced by mask topography. We demonstrate that low-n PSMs significantly enhance optical contrast and reduce line edge roughness, making them crucial for achieving high-resolution patterns at ultra-fine pitches. Additionally, we employ sophisticated SMO strategies, including asymmetric illumination and customized wavefront engineering, to further refine the lithographic process and improvements in normalized image log-slope (NILS) and focus control are achieved. Through comprehensive simulations and experimental validations, we show that the strategic combination of these technologies not only mitigates the intrinsic limitations of EUV but also enhances the overall lithographic process. Through wafer evaluation, we optimized the illumination system for low-n attPSM, significantly contributing to improved best focus (BF) uniformity across different pattern pitches. We achieved a 15% improvement in local critical dimension uniformity (LCDU) compared to the binary (BIN) mask, reducing the LCDU from 2.6 nm to 2.21 nm. The results confirm that these integrated approaches significantly improve the printability of intricate patterns while maintaining high throughput and manufacturing yield, setting the stage for future advancements in EUV lithography technology.

Biography

Sung-gye Lee works as an engineer at Samsung Electronics. He received BS and MS degrees in Materials Engineering from Soongsil University in 2018 and 2020, respectively. He joined the foundry process development team at the Samsung Electronics Semiconductor Research Center in 2021, where he participated in the development of 3nm GAA logic devices and secured the mass production process. From 2024 onwards, he has been contributing to technological innovation by participating in the development of the next-generation logic devices based on Resolution Enhancement Technology (RET).

Abstract

EUV lithography has already been applied by logic companies and major DRAM companies for several years. Initially, DRAM companies began applying it to one or several layers in the D1a phase, and the number of layers has been steadily increasing since D1b. This increase in the number of EUV lithography layers results in increased costs for DRAM companies. Therefore, EUV masks are required to be more cost-effective than existing DUV masks. Of course, there should be no NILS loss in EUV lithography. It is necessary to develop a customized EUV mask that reflects the needs of these photolithography processes and considers whether it can be realized in the mask manufacturing process. We will discuss which absorber materials should be selected for EUV mask development, considering the mentioned factors, and whether the selected absorber can be used for mask production.

Biography

“Euisang Park”, has been Head of Mask Process position at SK hynix company for 6 years with responsibility the front-end of mask process included DUV Mask and EUV Mask. This position produces masks for DUV and EUV and is responsible for developing EUV masks according to the technology roadmap. Park and four others received the Innovation Award from SK Group in 2024 for the development of Ru PSM EUV Mask.

”Park” received a Ph.D degree in material engineering field from Seoul National University School, Seooul, Republic of Korea and a M.S degree in electronic engineering field from the Kyungpook University School, Daegu, Republic of Korea. The paper “Atomic Layer Deposition of Nanocrystalline-As-Deposited (GeTe)x(Sb2Te3)1–x Films for Endurable Phase Change Memory” was selected as the cover image in the 2019 chemistry of materials journal.

Abstract

In advanced photolithography, optimizing the illumination source is critical to enhancing imaging performance and extending the resolution limits. This study proposes a physics-based, intuitive method to determine optimal illumination conditions by analyzing the diffraction pattern of a mask by point-source under normal-incidence conditions. The diffraction positions, especially the 0th and ±1st orders, are used to predict effective illumination regions within the sigma space. By assuming σ-radius circles centered at each diffraction order in the pupil plane, the intersection of these circles reveals candidate positions for optimal source placement. This approach is particularly effective for periodic patterns, where diffraction occurs along multiple directions. Furthermore, we discuss the implications of diffraction directionality on DOF (depth of focus) and NILS (normalized image log slope), providing guidelines for robust source optimization under various pitch conditions.

Biography

Sangjin Kim is a seasoned semiconductor engineer and researcher with more than 28 years of expertise in lithography and semiconductor process development. He began his career at Hynix in 1996, where he contributed to DRAM process development in the mask and advanced process teams. Later, he joined Samsung Semiconductor Research Center, where he led numerous world-first technology initiatives, in Resolution Enhancement Technology (RET), multi-patterning techniques (LELE, SADP, SAUP), NTD processes, and EUV-based logic device development.
From 2009 to 2024, he played a pivotal role in developing advanced logic nodes, covering from FinFET to GAA transistors. Currently, he serves as an Industry-Academic Cooperation Professor at Ajou University, focusing on semiconductor R&D, lithography process innovation, and mentoring students through hands-on field programs.

Abstract

This presentation will discuss recent developments in advanced packaging that are significant for the next generation of AI semiconductors. As AI chips strive to achieve higher performance, advanced packaging technologies play a pivotal role in meeting these demands. Three important packaging technologies will be highlighted: wafer-level interposers, 3D memory die stacking and die-to-wafer hybrid bonding. The talk will focus on the inspection and metrology challenges these technologies present, with a deeper dive into die-to-wafer hybrid bonding. We will explore the complex process control required to achieve high yield and reliability, and how state-of-the-art inspection tools are addressing the stringent sensitivity and precision requirements of AI semiconductor packaging. Attendees will gain insights into the critical role of high capture rates and accurate measurements in ensuring the success of these sophisticated packaging architectures.

Biography

Stephen Hiebert, with over 25 years at KLA Corporation, leads InSIGHT Group Marketing across advanced semiconductors, packaging, final components and IC substrates. Previously, he was senior director and leader of the Packaging-LED business segment in the LS-SWIFT Division. His expertise includes advanced packaging process control solutions for foundry, IDM, and OSAT customers with a focus on patterned wafer defect inspection. He received his BS in Engineering from University of California Los Angeles, MS in Engineering from Stanford University, and MBA from UCLA’s Anderson School of Management.

Abstract

Atomic force microscope (AFM) is a very useful instrument in characterizing nanoscale features, However, the original AFM design, based on piezo-tube scanner, had slow response and non-orthogonal behavior, inadequate to address the metrology needs of industrial applications. In addition, complex setting of operating parameters rendered AFM prohibitively inaccessible for in-fab automation. This talk will trace the key technological innovations that transpired at Park Systems throughout 2000s and 2010s to improve the accuracy and automation of AFM measurement: a flat scan system, feed-forward algorithm, Hann function, dual servo system, self-optimization of servo gain and set-point, etc. In the new AFM system, one only needs to set the scan area and the z servo error limit that corresponds to the degree of measurement quality. As a result, AFM has evolved into an ideal methodology for non-destructive sample scan with longer tip life, in various industry applications. Among them, the automatic defect review (ADR) AFM locates and images defects during wafer manufacturing. The key technological challenge here is the accurate transfer and remapping of defect map from optical inspection tool to AFM stage, if at all possible, without any reference marking. Past, present, and future roadmap of ADR solutions will be presented along with the technology node that has defined the need of evolving features in ADR AFM.

Biography

Dr. Young-Kook (Ryan) Yoo is the Chief Strategy Officer at Park Systems. Since he joined Park Systems at the beginning of 2005, he has led new business developments in the industrial sector, capturing and expanding the market potential of the inline industrial automated AFM products and solutions. Dr. Yoo’s current team develops and implements a comprehensive growth strategy, overseeing the company’s M&A agenda, targeting and negotiating business partnerships and investments. At Intematix, his first and previous employment, he was a founding scientist and VP of research and development, responsible for design and development of new combinatorial thin film deposition/screening tools and new nanomaterials discovery projects. Dr. Yoo has a Ph.D. in Physics from University of California at Berkeley and B.A. in Physics from University of Chicago.

Abstract

Since the advent of deep learning, image enhancement was one of the first applications of it to outperform classical algorithms, but this new approach poses a new challenge of acquiring massive amount of "labeled" data (i.e., clean ground truth images). In this talk, I will go over some of the works to overcome this challenge by using Stein's unbiased risk estimator (SURE) with no clean measurements in denoising (NeurIPS 2018, NeurIPS 2019, ICCV 2021), compressive sensing (CVPR 2019), low-dose CT (JSTSP 2020) as well as by developing novel network architectures with small amount of clean image - "real" degradation pairs for diverse image restoration tasks (CVPR 2023, ECCV 2024).

Biography

Prof. Se Young Chun received his B.S.E. degree in electical engineering from Seoul National University in 1999 and his Ph.D. degree in electrical engineering: systems from the University of Michigan - Ann Arbor in 2009. He was a research fellow at Harvard Medical School and also a research fellow at the University of Michigan - Ann Arbor. He has been with Ulsan National Institute of Science and Technology from 2013 to 2021 as an assistant / associate professor in the Department of Electrical Engineering / AI. Since 2021, he has joined the Department of Electrical and Computer Engineering and the Interdisciplinary Program in AI, Seoul National University, Seoul, South Korea, as an associate professor and now he is currently a professor. He is an associate editor of IEEE Transactions on Image Processing and a senior area editor of IEEE Transactions on Computational Imaging. He is a member of IEEE Bio Imaging and Signal Processing Technical Committee and an IEEE Biometrics Council Representative of IEEE Vehicular Technology Society since 2023. He was the recipient of the 2015 Bruce Hasegawa Young Investigator Medical Imaging Science Award from the IEEE Nuclear and Plasma Sciences Society. His research interests include computational imaging algorithms, generative diffusion models, multimodal foundation models for applications in medical and industrial imaging, computer vision and robotics. He has authored and coauthored 65 papers in SCIE journals or top AI conferences.

Abstract

e-beam has always been a well-established method to detect and characterize electrical and physical defects in R&D. Its ability to offer higher resolution compared to optical systems, different detection modes, and advanced detection and classification algorithms enables fast root-cause analysis and process improvements. However, traditional systems with one electron beam provide limited wafer-coverage due to the fundamental beam resolution versus current trade-off. As a result, e-beam had limited applications beyond R&D so far, with 3DNAND being the only exception where e-beam has been a cost-effective fab monitoring solution due to the larger feature sizes.

With the transition towards 3D architectures and smaller feature sizes in advanced Logic and DRAM nodes, the need for accurate, fast, and close to the root-cause defect detection during yield and HVM becomes more critical than ever. In this talk, we show that with the emergence of the eScan1100 multi-electron-beam systems and with novel detection methods and algorithms, we provide solutions able to meet the wafer-coverage capabilities required for cost-effective yield improvement and HVM excursion monitoring. We present data from DRAM and Logic applications. Lastly, we present potential synergies with metrology to enable identifying and preventing failure modes closer to their generation mechanisms.

Biography

Dr. Anagnostis Tsiatmas is the Head of Technology for HMI e-beam Inspection and Metrology in ASML. He has been working for ASML since 2015. He received his MSc in Electrical & Computer Engineering from the Aristotle University of Thessaloniki, Greece in 2009 and his Ph.D. in Optoelectronics from Southampton University, UK in 2013 with main research focus on metamaterials and plasmonics methods for the generation and manipulation of THz and sub-THz fields. Since he joined ASML, Dr. Tsiatmas has worked with different research and engineering teams on the productization of novel approaches utilizing illumination and detection techniques, target design, and advanced algorithms to measure device overlay, tilt in 3D structures, and other patterning parameters using optical scatterometric systems such as Yieldstar. This work has resulted in the introduction of the In-Device Metrology product line, which has been one of the first metrology products to utilize machine learning in semiconductor High Volume Manufacturing. Following the development of optical products, in 2022, Dr. Tsiatmas moved to electron beam systems for metrology and inspection. His main focus is on the physics of electron-device interaction for the signal formation of VC (Voltage Contrast) and BSE (Back-Scattered Electron) applications, the creation of techniques to improve the stability of electron-beam sources and electron-optics, and the productization of advanced learning methods/AI (Artificial Intelligence) for the extraction of patterning information from weak detected signals with main goal to improve the sensitivity and throughput of e-beam products.

As of this moment, Dr. Tsiatmas has coauthored more than 30 publications and holds more than 20 US patents. For the future, his focus will remain on inspection and metrology applications for the HVM semiconductor industry and the potential synergies between the two.

Abstract

In this talk, I will introduce the principles of near-field-based nano-spectroscopy and imaging techniques, including near-field scanning optical microscopy (NSOM), tip-enhanced Raman spectroscopy (TERS), and tip-enhanced photoluminescence (TEPL) imaging. In addition, recent advances in the characterization and analysis of nanoscale optical properties of semiconductor materials will be introduced. Furthermore, I will discuss the potential applications of near-field imaging and spectroscopy techniques in semiconductor metrology and inspection processes

Biography

Prof. Kyoung-Duck Park is an Associate Professor in the Department of Physics and the Department of Semiconductor Engineering (Joint Appointment) at Pohang University of Science and Technology (POSTECH), Korea. He received his Ph.D. in Physics from the University of Colorado at Boulder in 2017, following M.S. and B.S. degrees in Information and Communication Engineering from Inha University. Before joining POSTECH, he held faculty positions at UNIST and postdoctoral training at the University of Colorado.

His research focuses on nano-optics and quantum spectroscopy of low-dimensional materials, exploring strong light–matter interactions at the nanoscale. His group has pioneered several tip-enhanced and cavity-enhanced spectroscopic techniques, enabling single-exciton control, nanoscale exciton transport studies, and dynamic modulation of optical states in 2D semiconductors. He has published extensively in journals such as Nature Nanotechnology, Nature Materials, Physical Review Letters, Science Advances, Nature Communications, Advanced Materials, Light: Science & Applications, and many others.

He is a recipient of multiple national awards, including the Young Physicist Award from the Korean Physical Society, the Ministerial Commendation from the Ministry of Science and ICT, and the Gyeongbuk Science and Technology Award. He also serves as an adjunct professor at Yonsei University and a affiliated professor at the Institute for Basic Science (IBS).

Abstract

Recent advances in industrial and scientific AI have been leading a paradigm shift in manufacturing and maintenance processes. In this presentation, I will introduce our recent efforts to expedite the metrology and inspection (MI) process for lithography patterns by using industrial and scientific AI methods.

First, vision AI-powered MI will be presented for efficient die-to-database inspection. It includes the precise alignment of SEM images with the corresponding target layouts, image super-resolution to accelerate the imaging process, and hotspot prediction to minimize the inspection region. In particular, we focus on how to minimize manual labeling and the amount of data to train the model by considering the difficulty and cost of obtaining labeled data. Then, I will briefly introduce scientific AI-powered computational lithography that facilitates the design-analysis-inspection-optimization of the lithography process. It is developed to improve the performance of vision AI-powered MI tools by augmenting a training dataset with virtually generated lithography patterns in controllable pattern qualities.

Biography

Prof. Do-Nyun Kim has received his bachelor's (2000) and master's (2002) degrees from Seoul National University. He was a full-time instructor at the Korea Air Force Academy from 2002 to 2005. After receiving his Ph.D. (2009) in the Department of Mechanical Engineering at MIT, he worked as a postdoctoral associate in the Department of Biological Engineering at MIT. He joined as a faculty member in the Department of Mechanical Engineering at Seoul National University in 2013. He founded the NEXTMI Co., Ltd. in 2024 and has served as CEO since then. His research fields include industrial and scientific machine learning with a major focus on semiconductor manufacturing, structural DNA/RNA nanotechnology, and mechanical metamaterials.

Abstract

New dry etching technologies are being adopted alongside next-generation lithography development and are emerging as a key technology for the fabrication of next-generation DRAM, V-NAND, and logic devices. NGL(Next Generation Lithography + Patterning) 2025 is focusing on the field of patterning research to align with these global trends. Various patterning challenges associated with next-generation lithography processes were also highlighted at the 2025 SPIE Advanced Lithography+Patterning conference entitled Advanced Etch Technology and Process Integration for Nanopatterning, which was held prior to this symposium. In this talk, recent advances in dry etching technologies reported at the 2025 SPIE conference will be introduced briefly, including emerging dry etching techniques for EUV lithography, atomic layer etching, new plasma chemistries toward low-GWP gas, computational research, and recent AI-driven developments.

Biography

Yeon Ho Im, Ph.D., has been a professor at the School of Semiconductor and Chemical Engineering at Jeonbuk National University since 2005. He received his Ph.D. on plasma etching experiment and simulation from Jeonbuk National University, Jeonju, Korea in 2001. After completing his doctorate, he joined the Center for Gigascale Integration at Rensselaer Polytechnic Institute (USA) as a postdoctoral fellow, where he developed 3D feature scale simulator. Prior to joining Jeonbuk National University, he worked as a senior engineer in the Memory Division at SAMSUNG developing contact etch processes for DRAM and Flash memory. In 2014, he was a visiting scholar at Prof. Graves lab at the University of California, Berkeley (USA), where he conducted molecular dynamics simulation for plasma etching process.

Since 2009, he has made significant efforts to establish a plasma consortium in South Korea. As part of these efforts, he developed a commercialized software (K-SPEED) for 3D feature profile simulation of plasma etching and deposition processes, which is closely integrated with a plasma database and volume-averaged reactor-scale simulations. The volume-averaged reactor-scale simulation platform with plasma database was developed in institute of plasma technology at the Korea Institute of Fusion Energy. His main research interests include the development of cryogenic etching process using new chemistry, and high-aspect-ratio distortion through charge-up simulation.

Currently, he also serves as the director of the JBNU-ISRC (Inter-university Semiconductor Research Center at Jeonbuk National University), which seves as an education and testbed hub for semiconductor chemicals.

Abstract

To overcome the limitations of EUV patterning, ion beam processing technology is being developed to control the CD size with a directed ion beam. The ion beam processing suffers from difficulty in controlling the angle and charge accumulation on the wafer surface, which reduces the etch efficiency. By applying a hidden biasing method, the controllability of the ion beam incident angle was verified through the cross section of etching results, and the wafer surface was etched without a separate neutralizer by Applying a plasma source that can be discharged at low pressure. The etching results and ion beam current characteristics obtained by utilizing a low-pressure plasma source are reported.

Biography

Professor Shinjae You is a leading expert in plasma physics for semiconductor and display processing. He currently serves as a professor in the Department of Physics at Chungnam National University, South Korea. He earned his B.S. in Physics from Chungnam National University and received both his M.S. and Ph.D. in Plasma Physics from the Korea Advanced Institute of Science and Technology (KAIST).
Following his doctoral studies, Professor You conducted postdoctoral research at KAIST and POSTECH, and later served as a senior and distinguished research scientist at the Korea Research Institute of Standards and Science (KRISS).
His research focuses on electron and ion dynamics in low- and high-pressure plasmas, plasma diagnostics and simulations, high-density plasma source development, process control, and defect analysis. He has published extensively in peer-reviewed SCI journals and serves as a reviewer for several international academic publications.
Professor You has received numerous awards, including honors from the Samsung Human-Tech Paper Awards, the Korean Vacuum Society, and the Korean Society of Semiconductor & Display Technology. He is also actively involved in academic communities as an editorial board member, division chair, and evaluation committee member across various professional societies.

Abstract

The evolution of dry etching technology is accelerating to meet the stringent demands of sub-nanometer and 3D semiconductor device fabrication, which require precise etching such as high aspect ratio etch, tight critical dimension (CD) control and minimal device damage. To meet these demands, extreme low-pressure (sub-mTorr) and high-density plasma sources are necessary. While R-wave-based plasma sources such as Electron Cyclotron Resonance (ECR) and Helicon have been partially applied, their high magnetic field requirements, plasma instability at extreme low pressures, and wafer edge uniformity issues have limited their widespread adoption in mass production. On the other hand, the widely used ICP source faces limitations in operating at such extreme low pressures. To address these challenges, we introduce the Wave Enhanced ICP (WE-ICP) etcher, which combines the advantages of ECR and ICP plasmas. WE-ICP offers high-density, extreme low-pressure process capability with superior etch uniformity and plasma chemistry control, making it a promising solution for next-generation dry etch processes.

Biography

Dr. Taeho Shin is Vice President and Head of the Semiconductor Division at ICD Co., Ltd., where he leads the development and commercialization of advanced dry etchers for next-generation semiconductor manufacturing. With over 25 years of experience in plasma processing and dry etching technology, he has held key technical and leadership roles in both the United States and Korea.

He began his career at Applied Materials in California, serving as Technical Staff for a decade, where he contributed to the development and optimization of dry etcher hardware and processes at the forefront of the semiconductor industry. In 2007, he joined SEMES as Executive Director and Head of the Etch Business Division, leading the development aof dielectric and conductor dry etchers as well as MOCVD equipment.

He was an invited professor at Sungkyunkwan University, advising on advanced plasma technologies including ICP, Atomic Layer Etching, and magnetized plasma sources, while consulting for major companies such as SK hynix and supporting national semiconductor equipment initiatives. He also founded Gateway Equipment & Total Technology, a plasma etcher startup.

Dr. Shin has authored more than 15 technical papers and holds over 20 international patents in plasma etching and semiconductor process technologies. He received his Ph.D. in Materials Engineering from Stevens Institute of Technology, U.S.A., and his bachelor’s and master’s degrees in Nuclear Engineering from Hanyang University.

Abstract

High aspect ratio (HAR) etching has emerged as a major technical challenge in the manufacture of advanced semiconductor devices such as DRAM, V-NAND, and HBM. With the advent of 3D based next-generation devices, HAR etching is increasingly recognized as a key process and being integrated with various cutting-edge technologies such as cryogenic process with new chemistry. These trends limit scientific research due to unveiled complex physicochemical phenomena. To address this, we developed a universal surface reaction model and a charge accumulation model applicable to conventional or novel HAR etching processes. These models were integrated into the 3D simulation platform K-SPEED to enable predictive analysis of HAR etching profiles. Finally, we demonstrate that simulation research can progress in parallel with real plasma process development despite its inherent complexities.

Biography

Yeon Ho Im, Ph.D., has been a professor at the School of Semiconductor and Chemical Engineering at Jeonbuk National University since 2005. He received his Ph.D. on plasma etching experiment and simulation from Jeonbuk National University, Jeonju, Korea in 2001. After completing his doctorate, he joined the Center for Gigascale Integration at Rensselaer Polytechnic Institute (USA) as a postdoctoral fellow, where he developed 3D feature scale simulator. Prior to joining Jeonbuk National University, he worked as a senior engineer in the Memory Division at SAMSUNG developing contact etch processes for DRAM and Flash memory. In 2014, he was a visiting scholar at Prof. Graves lab at the University of California, Berkeley (USA), where he conducted molecular dynamics simulation for plasma etching process.

Since 2009, he has made significant efforts to establish a plasma consortium in South Korea. As part of these efforts, he developed a commercialized software (K-SPEED) for 3D feature profile simulation of plasma etching and deposition processes, which is closely integrated with a plasma database and volume-averaged reactor-scale simulations. The volume-averaged reactor-scale simulation platform with plasma database was developed in institute of plasma technology at the Korea Institute of Fusion Energy. His main research interests include the development of cryogenic etching process using new chemistry, and high-aspect-ratio distortion through charge-up simulation.

Currently, he also serves as the director of the JBNU-ISRC (Inter-university Semiconductor Research Center at Jeonbuk National University), which seves as an education and testbed hub for semiconductor chemicals.

Abstract

Advancing next-generation DRAM devices necessitates the development of novel lithographic materials and processes to extend the capability of extreme ultraviolet (EUV) single exposure technology (SET). In particular, realizing Low-NA EUV SET for contact layer patterning demands innovative strategies that go beyond conventional methodologies.
Although metal oxide resists (MORs) and dry development techniques have shown significant promise in line-space (L/S) and pillar applications, their application to contact patterning at sub-30 nm pitches has remained limited. In this study, hexagonal contact patterns were successfully formed by transitioning the reticle tone from dark to bright and optimizing the source-mask optimization (SMO) strategy, resulting in notable improvements in imaging performance.
The adoption of a bright-tone reticle required a negative tone development (NTD) process. MORs—owing to their high EUV absorptivity, exceptional resolution, and robust etch resistance—offered significant advantages over traditional chemically amplified resists (CARs). Additionally, plasma-assisted dry development improved scum defect control by leveraging the directionality of plasma exposure, yielding cleaner contact profiles.
These advancements led to a 50.5% improvement in normalized dose compared to the conventional CAR-based dark-field process, validating the combined effectiveness of MOR, NTD, dry development, and SMO. Continued process refinements—such as optimization of underlayer materials, resist thickness, post-exposure bake (PEB) conditions, and plasma development parameters—further enhanced dose efficiency and CD uniformity.
This study demonstrates the feasibility of extending Low-NA EUV SET to contact patterning and lays a critical foundation for transitioning EUV lithography toward High-NA platforms and enabling manufacturability at extreme design rules.

Biography

Jeonghee Choi is a Principal Engineer at the Semiconductor R&D Center of Samsung Electronics. She joined the company in 2005 after earning her B.S. in Chemical Engineering from Sungkyunkwan University. Since 2025, she has also been pursuing a graduate degree in Chemical and Biological Engineering at Seoul National University through Samsung’s SSIT talent development program, conducting research in Professor Joon Hak Oh’s laboratory on photo-crosslinkable materials and 3D gradient profile control for scalable manufacturing of stretchable electronics.

Her professional work spans over ten DRAM generations, where she has led lithography process and material development with a focus on resolution enhancement technologies (RET), ArF-based multi-patterning (MPT), and the integration of novel patterning materials.

From 2017, she led the development of EUV-based BLP Merge processes as the MEOL2 module leader and contributed to the EUV Low Dose Working Group for cost-effective high-volume EUV integration. As the technical lead of the Inorganic Resist Working Group from 2021, she contributed to the world’s first pre-production EUV-compatible Metal Oxide Resists (MOR), including spin-on and CVD-deposited types, gas-phase dry development, and novel CVD underlayers—breakthroughs that earned her the Samsung Best Paper Award and multiple patents. In 2024, she took on the role of task leader for the Extreme Lithography & Materials (ELM) team, driving next-generation R&D projects including advanced MOR, DSA for EUV rectification, High-NA EUV, and HBM patterning.

Abstract

The development of advanced patterning materials involves exploring vast chemical spaces, presenting significant challenges for conventional experimental approaches. We present IM-HAPPY(Inverse Model based on Hierarchically Abstracted rePeat unit of PolYmers), an artificial intelligence-driven platform designed to complement and accelerate next-generation patterning material development. IM-HAPPY employs a novel polymer representation system called HAPPY, which hierarchically abstracts complex polymer structures into simplified string formats while preserving essential chemical information. This approach addresses the data scarcity challenge that has limited machine learning applications in resist development. Our results suggest the valuable potential of artificial intelligence as a complementary tool in addressing challenges in semiconductor manufacturing, supporting more systematic materials innovation alongside experimental expertise.

Biography

Su-Mi Hur studied chemical engineering at Seoul National University (SNU, Korea) and obtained her Ph.D. at University of California, Santa Barbara (UCSB, USA). She continued her research career as a postdoctoral associate in Pritzker School of Molecular Engineering at the University of Chicago and Argonne National Laboratory. In 2015, she joined School of Polymer Science and Engineering at Chonnam National University (CNU, Korea) as an assistant professor and was promoted to a full professor in 2024. Her research is concerned with applying statistical mechanical theory and field-/particle-based coarse-grained simulations to investigate structural, thermodynamic, and dynamic phenomena in polymer-based soft materials. Her interests also lie in designing macromolecular systems and processes assisted with computational techniques including machine learning.

Abstract

Extreme scaling of semiconductor devices into the Angstrom era over the coming decades critically depends on advances in extreme ultraviolet (EUV) lithography. A key challenge in EUV patterning lies in the limited performance of current photoresist materials and the lack of associated fundamental understanding. In this talk, I will present our recent efforts on utilizing atomic layer deposition (ALD) techniques, including vapor-phase infiltration (VPI) and molecular ALD (MALD), for developing novel organic-inorganic hybrid EUV photoresist materials, which can feature proxy correlation between low-energy electron and EUV exposures, enhanced EUV sensitivity, high-resolution patterning capability, and improved etch selectivity.

Biography

Dr. Chang-Yong Nam is a Senior Scientist and Group Leader of the Electronic Nanomaterials Group at the Center for Functional Nanomaterials (CFN) at Brookhaven National Laboratory (BNL), and an Adjunct Professor of Materials Science and Engineering at Stony Brook University and University of Texas at Dallas. Dr. Nam received his Ph.D. in Materials Science and Engineering from the University of Pennsylvania (2007), M.S. in Materials Science and Engineering from KAIST (2001). and B.E. in Metallurgical Engineering from Korea University (1999). Dr. Nam’s research is focused on two primary areas: (a) Development of atomic layer processing (ALP) methods, including ALD and atomic layer etching (ALE), towards microelectronics and energy applications; (b) Materials processing and device physics in low-dimensional semiconductors and neuromorphic materials. Dr. Nam is the recipient of several honors, including the Brookhaven Science & Technology Awards (2024), the U.S. Department of Energy Accelerate Initiative Award (2023), Battelle Memorial Institute Inventor of the Year (2022), and Goldhaber Distinguished Fellowship (2007).

Abstract

Extreme-ultraviolet (EUV) photolithography is a game-changing technology for the fabrication of highly integrated semiconductors, enabling high-throughput patterning with critical dimensions at the nanometer scale. To unlock its full potential, the development of high-performance EUV photoresists (PRs) is essential. Our group has deployed synthetic research to address this need, focusing on ligand-engineered molecular resists incorporating EUV-active Sn and transition metal centers. We recently developed a first-generation EUV PR based on ladder-structured tetranuclear stannoxanes, which spontaneously assembled into pre-organized multilayers. This supramolecular architecture exhibited remarkable hydrolytic stability, maintaining structural integrity of the PR molecule in organic solutions for over a month. Under EUV irradiation, these materials generate negative-tone line/space patterns with a half-pitch resolution of 15 nm. To further enhance EUV lithographic sensitivity, we designed second-generation PR molecules bearing ligand tethering radical-generating sites. This molecular modification yielded a tenfold improvement in e-beam sensitivity (19 μC cm⁻² vs 190 μC cm⁻²), demonstrating the effectiveness of our modular design strategy. These initial results validate the viability of rational ligand engineering for advancing metal-based EUV resists. We anticipate that substantial performance gains remain accessible through continued synthetic innovation.

Biography

Youngmin You earned his bachelor and M.S. degrees in Chemical Engineering from Seoul National University. He then decided to move to Department of Materials Science and Engineering of Seoul National University for his Ph.D. study under supervision of Soo Young Park. Youngmin stayed at Massachusetts Institute of Technology as a Postdoctoral Fellow, where he learned bioinorganic chemistry under guidance of Stephen J. Lippard. He is currently Professor of Department of Chemical and Biomolecular Engineering at Yonsei University. His research group focuses on the design, syntheses, and spectroscopic investigations of transition metal complexes for photonic applications. Primary focus is placed on developing molecules for photolithography, electroluminescence, and photoredoxcatalysis.

Abstract

In this talk, we discuss the rational design and development of a main-chain scissionable functional copolymer platform by incorporating a photocleavable nitrobenzyl ester group into the middle of the copolymer backbone while fully preserving its overall structure and function for photopatterning applications on delicate organic semiconductor films. As a model system, a positive-tone photoimaging fluoroalkyl copolymer is used containing a photoisomerizable spiropyranyl unit. The nitrobenzyl ester functionality degrades under UV light and enhances solubility modulation and photopatternability by reducing chain length. This behavior is systematically studied across copolymers with varying, yet narrowly distributed, molecular weights. To further improve the sensitivity of the photoimaging copolymer, it is demonstrated that minimal structural modification of the cleavable group, specifically altering the positions of the methoxy and nitro groups, are highly effective. Finally, a square array of a chemically susceptible organic electron transport material, suitable for organic light-emitting diodes is fabricated using the copolymer through conventional lithography and pattern transfer processes. This work highlights the importance of rationally designing main-chain scission-type light-sensitive materials that maintain the core structure of conventional materials, making them highly compatible and desirable for standard organic electronic device fabrication processes.

Biography

Dr. Myungwoong Kim received his B.S. in Chemistry (2002) and M.S. in Physical Chemistry (2004) from Hanyang University under a guidance of Prof. Daewon Sohn. He then worked for several years in photopatterning materials industry. He completed his Ph.D. in Materials Science (2013) at University of Wisconsin – Madison under supervision of Prof. Padma Gopalan. He then conducted his postdoctoral research in Prof. Christopher K. Ober’s group at Cornell University. In 2015, he joined the Department of Chemistry at Inha University to begin his independent research career. His current research interests include precision polymer synthesis for desired structures and properties, surface and interface engineering, polymeric material designs for micro/nanofabrications, for functional gels, and for understanding polymer dynamics.

Abstract

As design pitch continues to decrease, research on sub-resolution assist feature (SRAF) is being conducted to secure sufficient patterning process margin. SRAF is a small pattern inserted around target patterns to improve the margin without being transferred to the wafer. To apply SRAF, Pre-validation is required using a simulation model that can predict whether SRAF will be transferred to the wafer. Commonly used model is difficult to predict SRAF printing accurately because it only includes information about critical dimension (CD), not SRAF. This talk will cover the new resist model with machine learning that learns both CD and SRAF information to improve the predictability of SRAF printing. Additionally, a new feature will be introduce which automatically generate SRAF gauges at precise location to improve the quality of SRAF data used for modeling. If this solution is reflected in the OPC verification process, we can expect the effect of preventing mask accidents by predicting defects caused by SRAF before manufacturing the mask.

Biography

Bokyoung Kim has been working in SK Hynix since 2018. She received B.S and M.S. in Chemical engineering at SungKyunKwan University in 2016 and 2018.
Since joining SK Hynix in 2018, she has worked on the development of new OPC(Optical Proximity Correction) technologies.
She have experience developing technologies for curvilinear OPC and optimization of mask stack, and are currently focusing on technologies and methods that can improve the predictability of models, including the SRAF printing prediction model.

Abstract

It is widely accepted recently that the benefit of curvilinear OPC outweighs the cost such as long runtime and bigger file size. But, the benefit was not clearly demonstrated for High NA cases.
In this paper, we will demonstrate that curvilinear OPC helps to improve the High NA pattering for both logic and DRAM cases. Also, we will show that the new format “Multigon” can help to mitigate the big file size issues.
Finally, we will provide a preliminary assessment of current mass variability and the implications for SRAF insertion.

Biography

Jung-Hoon has extensive knowledge in computational lithography with lots of field experiences. In Samsung semiconductor, he was one of the key members of the logic device OPC, RET, and DTCO (Design-Technology Co-optimization). Recently in ASML, he worked on EUV SMO, scanner imaging studies, DTCO, and OPC products development and improvement. He is currently a Director of Product management and marketing.

Detailed work experiences are as below:

• ASML, Brion, San Jose (2022~current): Director of Product management and marketing.
• ASML, Brion, San Jose (2014 – 2022): Principal product Engineer on OPC, and on SMO.
• Samsung Electronics (2007 – 2014), Korea: Principal Engineer, OPC team, SRD (Research center)
• Opticis (2001 – 2007), Korea: Principal Engineer
• KAIST (1989 – 2000), Korea: B.S. ~ Ph.D. in Physics

Abstract

Manhattan OPC has become insufficient to provide acceptable pattern fidelity. Curvilinear masks have been introduced as a solution to further reduce edge placement error and improve process variation band. While inverse lithography technology (ILT) can generate high-quality curvilinear masks, its high computational cost and the generation of non-manufacturable noise limit its use in industry. As a practical alternative, curvilinear OPC has emerged. Correction is still performed segment by segment, while each segment is assumed as a curve instead of a straight line.

This talk begins with a technical review of curvilinear OPC, highlighting current approaches such as heuristic curve point adjustment, Manhattan-curvilinear hybrid OPC flows, and ILT-initialized refinement. A machine learning-guided approach, which we have recently proposed, is then presented, integrating U-Net-based re-fragmentation and manufacturability-aware curve correction to improve OPC performance and runtime. The talk concludes with some insights into the role of machine learning-based OPC in future computational lithography.

Biography

Seohyun Kim is a Ph.D. student in the School of Electrical Engineering at KAIST, where she also received her B.S. and M.S. degrees. She is advised by Prof. Youngsoo Shin, and her research lies in computational lithography and design-technology co-optimization (DTCO), with a particular focus on curvilinear optical proximity correction (OPC) and machine learning-based mask optimization.

She is the first author of multiple peer-reviewed papers on ML-guided curvilinear OPC, including techniques for re-fragmentation, curve correction, and critical segment classification. She also works on the synthesis of critical mask patterns to enhance lithography simulation. Her recent work has been published in IEEE Transactions on Semiconductor Manufacturing and SPIE Advanced Lithography, and was recognized with the ISE President Best Paper Award at ISOCC 2024. Her research aims to enable fast, accurate, and manufacturable OPC through the integration of machine learning-based optimization.

Abstract

Phase Shift Mask (PSM) technology has been extensively studied as a promising solution to enhance the patterning capability of EUV lithography, particularly in the context of tightening design rules and increasing feature density. One of the critical challenges in applying PSM to EUV is the best focus shift phenomenon, which can lead to CD variation and reduced process margins, especially when multiple pitches are involved. In this presentation, we investigate the root causes of best focus shift observed in PSM-based EUV patterning using rigorous 3D mask simulations. By systematically analyzing the phase effects and topographical mask structures, we identify key factors contributing to this shift. Based on these findings, several optimization strategies are proposed to enable robust co-patterning of various pitch contact arrays, thereby improving pattern fidelity and focus stability across the die. Furthermore, this work examines the role of sub-resolution assist features (SRAF) in mitigating 3D mask effects in PSM. Simulation results show that carefully designed SRAF can effectively reduce aerial image distortions and enhance overall CD control. The benefits of PSM over binary intensity mask (BIN) approaches are also highlighted, particularly in terms of CD uniformity and across-pitch patterning consistency. Through this study, we aim to provide practical insights into the implementation of EUV PSM for logic device applications, and to contribute to the development of more robust and extendable lithographic solutions for next-generation technology nodes.

Biography

Eun Sung Kim joined Samsung Electronics in 2014, where she is currently a Principal Engineer. She received her B.S. degree in Electrical and Electronic Engineering from Hanyang University in 2007, and her M.S. and Ph.D. degrees in Electrical Engineering from KAIST in 2009 and 2014, respectively. Her doctoral research focused on the implementation and analysis of surface plasmon lithography.

Upon joining the Semiconductor R&D Center at Samsung Electronics in 2014, she worked as a staff engineer in the OPC (Optical Proximity Correction) team for memory devices, focusing on modeling. In 2020, she shifted her focus to OPC development for logic devices, and from 2021, she spent two years at the IBM Research Alliance in Albany, USA, where she contributed to logic product pathfinding efforts. Her current research interests include logic device OPC, next-generation mask technology, overlay solutions, and High-NA lithography modeling.

Abstract

Semiconductor lithography is essential for integrated circuit manufacturing, where precise aerial image prediction is critical to ensure pattern fidelity. Conventional optical imaging models such as Abbe and Hopkins provide accurate simulations but are computationally expensive for large-scale layouts. This paper proposes a physics-informed neural network (PINN) framework that incorporates optical physics directly into the training process to enable fast and accurate aerial image prediction. By embedding physical constraints into the loss function, the method reduces dependency on large training datasets and improves generalization across varying layout geometries and illumination conditions. The model is validated on both standard lithographic patterns and full-chip semiconductor layouts under ArF immersion (193 nm) and EUV (13.5 nm) exposure. Results show that the proposed approach significantly reduces computation time while maintaining sub-nanometer accuracy. Furthermore, we demonstrate its effectiveness in inverse lithography technology (ILT), achieving improved mask optimization and edge placement accuracy in optical proximity correction (OPC). This work provides a scalable and efficient solution for advanced computational lithography.

Biography

Jinho Lee is a Principal Engineer with dual affiliations at Samsung Electronics and Seoul National University. He received his B.S. and M.S. degrees in Mechanical Engineering from Yonsei University in 2008 and 2010, respectively. In 2025, he earned his Ph.D. in Mechanical Engineering from Seoul National University, where he focused on physics-informed neural networks and computational lithography.

Since joining Samsung Electronics in 2010, he has been working as a process development engineer in the Semiconductor R&D Center. His research interests include computational lithography, photoresist modeling, and machine learning-based optimization techniques for advanced patterning. He has contributed to various technology nodes by integrating physics-based simulation with AI-assisted process design to improve pattern fidelity and manufacturability.

Abstract

Transfer printing technology offers significant advancements for the electronics and display industry by enabling the precise transfer and integration of microscale devices and materials onto various substrates. This technology particularly supports the high-resolution assembly of micro-LED arrays, crucial for creating displays with superior brightness, color accuracy, and energy efficiency. The speaker will discuss the results of his recent research into transfer printing for micro-LED assembly in this talk. Specifically, he presents a shape memory polymer (SMP)-based transfer printing that facilitates the transfer of micro-LEDs and related challenges towards micro-LED display manufacturing.

Biography

Seok Kim received his B.S. from Pohang University of Science and Technology (POSTECH) in South Korea, M.S. from University of California at Los Angeles, and Ph.D. from Carnegie Mellon University, all in mechanical engineering. After his academic training, he joined the faculty at the University of Illinois at Urbana-Champaign where he was tenured. After that, he moved and is currently a professor at POSTECH. His current research interests include: 1) biomimetic design of smart surfaces for reversible dry adhesion, tunable wetting and light manipulation, 2) transfer printing-based heterogeneous integration, microassembly, and nanomanufacturing, 3) 3D MEMS fabrication technologies. He was a recipient of the National Science Foundation CAREER Award, the ASME Chao and Trigger Young Manufacturing Engineer Award, and the Young Investigator Grant Award from the Korean–American Scientists and Engineers Association.

Abstract

Achieving high-efficiency electrocatalysis requires precise control over catalyst geometry, surface chemistry, and mass transport pathways. Conventional nanostructuring approaches often struggle to simultaneously optimize these parameters at the nanoscale. In this talk, we present a nanotransfer printing (nTP)-based 3D nanofabrication platform that enables the creation of well-defined, high-aspect-ratio nanoscale architectures with controlled spatial organization across large areas. By leveraging nTP, we fabricate 3D catalyst structures that promote enhanced mass transport via engineered porosity and hierarchical flow channels, mitigating concentration polarization and improving reactant accessibility to active sites. The process enables deterministic placement of nanoscale features, ensuring uniformity and reproducibility. Electrochemical characterization reveals significant improvements in current density, turnover frequency, and Faradaic efficiency for reactions including hydrogen evolution, oxugen evolution, and CO₂ reduction, directly attributable to the enhanced mass transport and increased triple-phase boundaries enabled by the 3D architecture. We also demonstrate how this fabrication strategy integrates with scalable manufacturing workflows, offering a pathway to bridge nanoscale design with device-level implementation.

Biography

Yeon Sik Jung is a full professor in the department of materials science and engineering at the Korea Advanced Institute of Science and Technology (KAIST). He earned his Ph.D. in Materials Science and Engineering from the Massachusetts Institute of Technology (MIT) and completed postdoctoral research at the Lawrence Berkeley National Laboratory. His research interests include nanostructure fabrication via molecular self-assembly, nanotransfer printing (nTP), and their applications in semiconductor manufacturing, displays, surface-enhanced Raman spectroscopy, and electrocatalysis. Prof. Jung has authored over 200 journal articles and holds more than 50 patents mostly in nanofabrication and materials science.

Abstract

Photolithography remains a cornerstone in high-resolution microfabrication for electronics, yet its dependence on chemical solvents restricts the integration of emerging nanomaterials such as quantum dots and 2D materials. To overcome this limitation, we introduce a dry photoresist pattern transfer method using a viscoelastic polymeric stamp. This approach removes solvent constraints and expands material and substrate compatibility.

The process entails forming a photoresist layer on PDMS through conventional photolithography, then transferring the patterned film onto diverse substrates—even those with complex topologies—via contact printing. Subsequent nanomaterial deposition followed by PR lift-off achieves precise pattern definition.

This solvent-free technique supports varied coating methods, including dip-coating, drop-casting, and spin-coating, and facilitates patterning on curved surfaces—ideal for flexible and wearable devices. Additionally, negative photoresists utilized in this process improve chemical durability, enabling multilayer fabrication.We validate the method’s high-resolution capabilities and its adaptability across substrate types. In future work, we aim to integrate sensing materials using electrospray deposition, demonstrating the platform’s potential for advanced sensor applications. Altogether, this novel dry transfer strategy offers scalable, versatile micropatterning for next-generation electronic devices.

Biography

Hohyun Keum earned both his Bachelor’s and Ph.D. degrees in Mechanical Engineering from the University of Illinois at Urbana-Champaign. His doctoral research centered on transfer-printing-based micromanufacturing, with a focus on developing process protocols that enable diverse materials to be formatted for transfer and integrated into microelectromechanical systems.
Following graduation, he joined LG Display’s Advanced Development Team, where he led investigations into micro-LED technologies for flexible and stretchable display applications.
Currently, Dr. Keum serves as a researcher at the Korea Institute of Industrial Technology (KITECH), specializing in additive micromanufacturing techniques aimed at advancing next-generation mechanical and electronic devices. He also actively supports venture entrepreneurs in developing and commercializing cutting-edge biosensing technologies.

Abstract

Next-generation AR/VR systems demand ultrahigh-resolution, energy-efficient, and deformable displays, for which quantum dot light-emitting diodes (QLEDs) are highly promising due to their excellent photoluminescence quantum yield, wide color gamut, and high color purity. In this talk, we introduce a double-layer transfer printing technique that enables the fabrication of high-efficiency and high-definition QLEDs by co-transferring densely packed QD and ZnO nanoparticle layers. By tailoring the surface properties of viscoelastic stamps, this approach achieves RGB pixelated arrays with resolutions up to 2,565 PPI and monochromatic patterns exceeding 20,000 PPI, far surpassing the resolution requirements of AR/VR microdisplays. The compact heterolayer structure significantly suppresses leakage current and improves charge injection balance, resulting in a record-high external quantum efficiency of 23.3%. Moreover, the process is compatible with flexible and wearable substrates, offering a scalable route toward full-color, skin-conformal QLED displays and unlocking new possibilities for next-generation display technologies.

Biography

Prof. Moon Kee Choi is an Associate Professor in the Department of Materials Science and Engineering at UNIST (Ulsan National Institute of Science and Technology), Republic of Korea. She received her B.S. and Ph.D. in Chemical and Biological Engineering from Seoul National University, followed by postdoctoral research at the Institute for Basic Science (IBS) and the University of California, Berkeley. Her research focuses on nanomaterials-based flexible and stretchable optoelectronic devices, including quantum dot and perovskite light-emitting diodes, high-resolution displays, soft robotics, and skin-attachable sensors for wearable healthcare monitoring systems. She is particularly interested in developing advanced transfer printing and interfacial engineering strategies for next-generation deformable electronic platforms.

Abstract

Understanding and controlling brain-body dynamics requires advanced technologies capable of recording and stimulating neural signals across diverse internal organs. However, current neural interface technologies face critical limitations, including lack of cell-type specificity, high invasiveness, poor long-term biocompatibility, and structural rigidity that restricts access to peripheral targets. These constraints hinder precise modulation and chronic monitoring of the nervous system. To address these challenges, we present a novel class of flexible and stretchable fiber-based neural probes engineered for seamless integration with neural tissues. Leveraging a scalable thermal drawing process (TDP), we fabricate multifunctional neural interfaces with extended length, mechanical softness, and modular functionality. This platform enables chronic brain-machine interfacing with improved longevity and performance. The use of diverse material systems—including polymers, elastomers, hydrogels, and liquid metals—enables precise control over fiber properties such as conductivity, optical guidance, and fluidic delivery. I will discuss how these material and structural innovations facilitate stable, long-term in vivo operation, and how they can be tailored for targeted interactions with specific nerves.

Biography

Seongjun Park received the B.S. degree in Mechanical and Aerospace Engineering from Seoul National University, Seoul, South Korea, in 2013, and the M.S. degree in Mechanical Engineering and the Ph.D. degree in Electrical Engineering and Computer Science from the Massachusetts Institute of Technology (MIT), Cambridge, MA, USA, in 2015 and 2018, respectively. He was previously an Assistant Professor in the Department of Bio and Brain Engineering at the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, South Korea. He is currently an Associate Professor at the School of Transdisciplinary Innovations and the College of Medicine, Seoul National University. His research interests include the development of biomedical and neural interfaces using fibers and soft materials for neural investigation, sensory/motor restoration, electrical medicine, and tissue engineering.

Abstract

Despite the substantial progress being made in Si-based light modulation and detection and their large-scale, cost-effective, monolithic device integration technology, the realization of small, efficient, and reliable on-chip integrated light sources, for example, continuous-wave (CW) III-V semiconductor nanolasers and electrically driven micro-/nanoLEDs on Si at room temperature (RT) has remained a challenge due to the lack of appropriate integration schemes. Here, we introduce a simple, easy and damage-free micro-transfer-based manipulations that enables the realizations of on-demand Si-integrable RT CW nanolasers, electrically driven on-chip transferrable micro-/nanoLEDs and vertically heterogeneous integrable three-dimensional (3D) III-V/Si micro-resonators/light sources. A smartly designed InGaAsP gain structure in conjunction with an individually addressable and highly precise on-demand gain-printing technique addresses several key technological issues, demonstrating the RT CW operation with a low-thresholds of ~50 µW, the all-graphene-contact-assisted electroluminescence, and the spontaneous emission and its enhancement in 3D wood-pile-type PhC nanocavities. A simple demonstration of the on-demand gain-printing and the integrated Si-integrable light sources exhibit the potential of wide and ubiquitous adoption in Si photonics and photonic integrated circuit (PIC) communities.

Biography

You-Shin No received his B.S and Ph.D. degrees in Department of Physics from Korea University, Seoul, Korea, in 2008 and 2014, respectively. He worked as a post-doctoral fellow in the Department of Chemistry and Chemical Biology at Harvard (2014-2017). He became an assistant professor in the Department of Physics at Konkuk University (2017-2021). He became an associate professor in the same department in 2021 (2021-present) and served as a department chair (2022-2024). His research interests include key photonic elements and integrated photonic circuits and systems. In particular, his group focuses on the development of III-V/Si heterogeneous/hybrid and three-dimensional (3D) vertical integration and manipulation technologies, and the development of ultimate light sources at nanoscale (e.g., nanolasers, nanoLEDs, nano-emitters, etc.) and its on-chip, on-demand integration.

Abstract

As semiconductor devices become increasingly miniaturized and functionally diverse, conventional 2D integration approaches are reaching fundamental limits in terms of scalability, power efficiency, and form factor. Monolithic 3D integration, where functional layers are vertically stacked and seamlessly interconnected, offers a promising pathway to overcome these challenges. In particular, the use of freestanding single-crystalline membranes enables heterogeneous integration of high-performance materials onto arbitrary substrates, without being constrained by lattice mismatch or thermal budget issues. These membranes can serve not only as building blocks for transistors and memory, but also as platforms for high-sensitivity sensors and in-sensor computing elements. Importantly, this approach is fully compatible with advanced lithography techniques, as it allows functional membranes to be transferred prior to device fabrication. This eliminates the need for layer-to-layer alignment at the stacking stage, enabling the retention of high-resolution patterning across vertically integrated layers. By leveraging techniques such as remote epitaxy and layer release, this strategy unlocks new opportunities for compact, multifunctional, and lithography-compatible devices, with applications ranging from healthcare monitoring to environmental sensing and beyond.

Biography

Jun Min Suh is an Assistant Professor in the School of Transdisciplinary Innovations (Intelligent Semiconductor Systems Major) and the Department of Materials Science and Engineering at Seoul National University. He received his B.S. and Ph.D. degrees in Materials Science and Engineering from Seoul National University in 2014 and 2020, respectively. He worked as a postdoctoral researcher at Seoul National University (2020–2021) and the Massachusetts Institute of Technology (2021–2025). His research focuses on the development of advanced multifunctional monolithic 3D integration systems from both materials and device perspectives.